`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:27:52 07/02/2015 
// Design Name: 
// Module Name:    Etapa3 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Etapa3(
	input RegDst,
	input RegWriteO,
	input ALUSrc, 
	input PCSrc,
	input MemRead,
	input [3:0] MemWrite,
	input MemToReg,
	input [1:0] ALUOp, 
	input [2:0] LoadOp,
	input [1:0] StoreOp,
	input [2:0] InmCtrl,
	input [31:0] E2Adder,
	input [31:0] ReadData1,
	input [31:0] ReadData2,
	input [31:0] ExtSig,
	input [4:0] RT,
	input [4:0] RD,
	input jmpIn,
	input [31:0] DataE4,
	input [31:0] DataE5,
	input [1:0] forwardA,
	input [1:0] forwardB,
	output jmpOut,
	output [31:0] salidaALU,
	output zeroFlag,
	output [31:0] salidaAdder,
	output [4:0] salidaMux,
	output [31:0] Data2,
	output RegWrite,
	output PCSrc1,
	output MemRead1,
	output [3:0] MemWrite1,
	output MemToReg1,
	output [2:0] LoadOp1
    );

wire [31:0] Bop;
wire [31:0] add;
wire [4:0] shift;
wire [5:0] control;
wire [31:0] outForA;
wire [31:0] AluA;
wire [31:0] outForB;
wire [31:0] AluB;
//assign Data2 = ReadData2;
assign RegWrite = RegWriteO;
assign PCSrc1 = PCSrc;
assign MemRead1 = MemRead;
assign MemWrite1 = MemWrite;
assign MemToReg1 = MemToReg;
assign LoadOp1 = LoadOp;
assign jmpOut = jmpIn;



ALU alu(
.A(AluA),
.B(AluB),
.COD_OP(control),
.SA(shift),
.C(salidaALU),
.Zero(zeroFlag)
);

ALUControl ALUc(
.ALUOp(ALUOp),
.funct(ExtSig[5:0]),
.SAIn(ExtSig[10:6]),
.SAOut(shift),
.InmCtrl(InmCtrl),
.OutALUCtrl(control)
);

Adder adder(
.In1(E2Adder),
.In2(add),
.out(salidaAdder)
);

Mux2to15bits muxReg(
.Input1(RT),
.Input2(RD),
.sel(RegDst),
.Out(salidaMux)
);

Mux2to1 AluSignOrReg(
.Input1(ReadData2),
.Input2(ExtSig),
.sel(ALUSrc),
.Out(Bop)
);

Mux2to1 ForA(
.Input1(DataE4),
.Input2(DataE5),
.sel(forwardA[0]),
.Out(outForA)
);

Mux2to1 AAlu(
.Input1(ReadData1),
.Input2(outForA),
.sel(forwardA[1]),
.Out(AluA)
);

Mux2to1 BAlu(
.Input1(Bop),
.Input2(outForB),
.sel(forwardB[1]),
.Out(AluB)
);

Mux2to1 ForB(
.Input1(DataE4),
.Input2(DataE5),
.sel(forwardB[0]),
.Out(outForB)
);

ShiftLeft2 shifer(
.in(ExtSig),
.out(add));

StoreControlUnit StoreControl(
.in(ReadData2),
.out(Data2),
.ctrl(StoreOp)
);

endmodule
